Simulating a Multi-core x86_64 Architecture with Hardware ISA Extension Supporting a Data-Flow Execution Model

TitoloSimulating a Multi-core x86_64 Architecture with Hardware ISA Extension Supporting a Data-Flow Execution Model
Publication TypeConference Paper
Year of Publication2014
AuthorsHo, N., A. Portero, M. Solinas, A. Scionti, A. Mondelli, P. Faraboschi, and R. Giorgi
Conference NameIEEE 2nd International Conference on Artificial Intelligence, Modeling and Simulation (AIMS)
Date Published11/2014
Conference LocationMadrid, Spain